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| 3 nV/Hz Ultralow Distortion, High Speed Op Amp AD8045 FEATURES Ultralow distortion SFDR -101 dBc @ 5 MHz -90 dBc @ 20 MHz -63 dBc @ 70 MHz Third-order intercept 43 dBm @ 10 MHz Low noise 3 nV/Hz 3 pA/Hz High speed 1 GHz, -3 dB bandwidth (G = +1) 1350 V/s slew rate 7.5 ns settling time to 0.1% Standard and low distortion pinout Supply current: 15 mA Offset voltage: 1.0 mV max Wide supply voltage range: 3.3 V to 12 V APPLICATIONS Instrumentation IF and baseband amplifiers Active filters ADC drivers DAC buffers CONNECTION DIAGRAMS NC FEEDBACK -IN +IN 1 2 3 4 8 7 6 5 +VS OUTPUT NC -VS 04814-0-001 Figure 1. 8-Lead AD8045 LFCSP (CP-8) FEEDBACK 1 -IN 2 +IN 3 -VS 4 8 NC +VS OUTPUT NC 04814-0-001 7 6 5 Figure 2. 8-Lead AD8045 SOIC/EP (RD-8) GENERAL DESCRIPTION The AD8045 is a unity gain stable voltage feedback amplifier with ultralow distortion, low noise, and high slew rate. With a spurious-free dynamic range of -90 dBc @ 20 MHz, the AD8045 is an ideal solution in a variety of applications, including ultrasound, ATE, active filters, and ADC drivers. ADI's proprietary next generation XFCB process and innovative architecture enables such high performance amplifiers. The AD8045 features a low distortion pinout for the LFCSP, which improves second harmonic distortion and simplifies the layout of the circuit board. The AD8045 has 1 GHz bandwidth, 1350 V/s slew rate, and settles to 0.1% in 7.5 ns. With a wide supply voltage range (3.3 V to 12 V) and low offset voltage (200 V), the AD8045 is an ideal candidate for systems that require high dynamic range, precision, and high speed. The AD8045 amplifier is available in a 3 mm x 3 mm LFCSP and the standard 8-lead SOIC. Both packages feature an exposed paddle that provides a low thermal resistance path to the PCB. This enables more efficient heat transfer, and increases reliability. The AD8045 works over the extended industrial temperature range (-40C to +125C). -20 G = +1 -30 VS = 5V VOUT = 2V p-p -40 RL = 1k RS = 100 -50 -60 -70 -80 HD3 LFCSP -90 -100 -110 -120 0.1 04814-0-079 HARMONIC DISTORTION (dBc) HD2 LFCSP 1 10 FREQUENCY (MHz) 100 Figure 3. Harmonic Distortion vs. Frequency for Various Packages Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved. AD8045 TABLE OF CONTENTS Specifications with 5 V Supply ..................................................... 3 Specifications with +5 V Supply ..................................................... 4 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution.................................................................................. 5 Pin Configurations and Function Descriptions ........................... 6 Typical Performance Characteristics ............................................. 7 Circuit Configurations................................................................... 16 Wideband Operation ................................................................. 16 Theory of Operation ...................................................................... 17 Frequency Response................................................................... 17 DC Errors .................................................................................... 17 Output Noise............................................................................... 18 Applications..................................................................................... 19 Low Distortion Pinout............................................................... 19 High Speed ADC Driver ........................................................... 19 90 MHz Active Low-Pass Filter (LPF) ..................................... 20 Printed Circuit Board Layout ....................................................... 22 Signal Routing............................................................................. 22 Power Supply Bypassing ............................................................ 22 Grounding ................................................................................... 22 Exposed Paddle........................................................................... 23 Driving Capacitive Loads.......................................................... 23 Outline Dimensions ....................................................................... 24 Ordering Guide .......................................................................... 24 REVISION HISTORY 9/04--Data Sheet Changed from Rev. 0 to Rev. A Changes to Features......................................................................... 1 Changes to Specifications ............................................................... 4 Changes to Figure 58..................................................................... 15 Changes to Figure 63..................................................................... 17 Changes to Frequency Response Section ................................... 17 Changes to Figure 64..................................................................... 17 Changes to DC Errors Section..................................................... 17 Changes to Figure 65..................................................................... 17 Changes to Figure 66..................................................................... 18 Changes to Output Noise Section ............................................... 18 Changes to Ordering Guide ......................................................... 24 7/04--Revision 0: Initial Version Rev. A | Page 2 of 24 AD8045 SPECIFICATIONS WITH 5 V SUPPLY TA = 25C, G = +1, RS = 100 , RL = 1 k to ground, unless noted otherwise. Exposed paddle must be floating or connected to -VS. Table 1. Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Conditions G = +1, VOUT = 0.2 V p-p G = +1, VOUT = 2 V p-p G = +2, VOUT = 0.2 V p-p G = +2, VOUT = 2 V p-p, RL = 150 G = +1, VOUT = 4 V step G = +2, VOUT = 2 V step fC = 5 MHz, VOUT = 2 V p-p LFCSP SOIC fC = 20 MHz, VOUT = 2 V p-p LFCSP SOIC fC = 70 MHz, VOUT = 2 V p-p LFCSP SOIC f = 100 kHz f = 100 kHz NTSC, G = +2, RL = 150 NTSC, G = +2, RL = 150 Min Typ 1000 350 400 55 1350 7.5 Max Unit MHz MHz MHz V/s ns 300 320 1000 Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE Harmonic Distortion (dBc) HD2/HD3 -102/-101 -106/-101 -98/-90 -97/-90 -71/-71 -60/-71 3 3 0.01 0.01 0.2 8 2 8 0.2 64 3.6/1.0 1.3 3.8 -91 8 -3.9 to +3.9 -3.6 to +3.6 70 90/170 18 5 16 -68 -73 6 19 1.0 6.3 1.3 dBc dBc dBc dBc dBc dBc nV/Hz pA/Hz % Degrees mV V/C A nA/C A dB M pF V dB ns V V mA mA pF V mA dB dB Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Bias Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection OUTPUT CHARACTERISTICS Output Overdrive Recovery Time Output Voltage Swing Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current Positive Power Supply Rejection Negative Power Supply Rejection See Figure 54 VOUT = -3 V to +3 V Common-mode/differential Common-mode VCM = 1 V VIN = 3 V, G = +2 RL = 1 k RL = 100 Sinking/sourcing 30% overshoot, G = +2 62 -83 -3.8 to +3.8 -3.4 to +3.5 1.65 +VS = +5 V to +6 V, -VS = -5 V +VS = +5 V, -VS = -5 V to -6 V -61 -66 Rev. A | Page 3 of 24 AD8045 SPECIFICATIONS WITH +5 V SUPPLY TA = 25C, G = +1, RS = 100 , RL = 1 k to midsupply, unless otherwise noted. Exposed paddle must be floating or connected to -VS. Table 2. Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Conditions G = +1, VOUT = 0.2 V p-p G = +1, VOUT = 2 V p-p G = +2, VOUT = 0.2 V p-p G = +2, VOUT = 2 V p-p, RL = 150 G = +1, VOUT = 2 V step G = +2, VOUT = 2 V step fC = 5 MHz, VOUT = 2 V p-p LFCSP SOIC fC = 20 MHz, VOUT = 2 V p-p LFCSP SOIC fC = 70 MHz, VOUT = 2 V p-p LFCSP SOIC f = 100 kHz f = 100 kHz NTSC, G = +2, RL = 150 NTSC, G = +2, RL = 150 Min Typ 900 200 395 60 1060 10 Max Unit MHz MHz MHz MHz V/s ns 160 320 480 Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE Harmonic Distortion (dBc) HD2/HD3 -89/-83 -92/-83 -81/-70 -83/-70 -57/-46 -57/-46 3 3 0.01 0.01 0.5 7 2 7 0.2 63 3/0.9 1.3 1.2 to 3.8 -94 10 1.1 to 4.0 1.2 to 3.8 55 70/140 15 5 15 -67 -73 12 18 1.4 6.6 1.3 dBc dBc dBc dBc dBc dBc nV/Hz pA/Hz % Degrees mV V/C A nA/C A dB M pF V dB ns V V mA mA pF V mA dB dB Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Bias Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection OUTPUT CHARACTERISTICS Output Overdrive Recovery Time Output Voltage Swing Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current Positive Power Supply Rejection Negative Power Supply Rejection See Figure 54 VOUT = 2 V to 3 V Common-mode/differential Common-mode VCM = 2 V to 3 V VIN = -0.5 V to +3 V, G = +2 RL = 1 k RL = 100 Sinking/sourcing 30% overshoot, G = +2 61 -78 2.2 to 3.7 2.5 to 3.5 3.3 +VS = +5 V to +6 V, -VS = 0 V +VS = +5 V, -VS = 0 V to -1 V -65 -70 Rev. A | Page 4 of 24 AD8045 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage Power Dissipation Common-Mode Input Voltage Differential Input Voltage Exposed Paddle Voltage Storage Temperature Operating Temperature Range Lead Temperature Range (Soldering 10 sec) Junction Temperature Rating 12.6 V See Figure 4 -VS - 0.7 V to +VS + 0.7 V VS -VS -65C to +125C -40C to +125C 300C 150C The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the die due to the AD8045 drive at the output. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). PD = Quiescent Power + (Total Drive Power - Load Power) V V PD = (VS x I S ) + S x OUT 2 RL VOUT 2 - RL Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RMS output voltages should be considered. If RL is referenced to -VS, as in single-supply operation, the total drive power is VS x IOUT. If the rms signal levels are indeterminate, consider the worst case, when VOUT = VS/4 for RL to midsupply. PD = (VS x I S ) + (VS / 4 )2 RL THERMAL RESISTANCE JA is specified for the worst-case conditions, i.e., JA is specified for device soldered in circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type SOIC LFCSP JA 80 93 JC 30 35 Unit C/W C/W In single-supply operation with RL referenced to -VS, worst case is VOUT = VS/2. Airflow increases heat dissipation, effectively reducing JA. Also, more metal directly in contact with the package leads and exposed paddle from metal traces, through holes, ground, and power planes reduce JA. Figure 4 shows the maximum safe power dissipation in the package versus the ambient temperature for the exposed paddle SOIC (80C/W) and LFCSP (93C/W) package on a JEDEC standard 4-layer board. JA values are approximations. 4.0 Maximum Power Dissipation The maximum safe power dissipation for the AD8045 is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150C, which is the glass transition temperature, the properties of the plastic change. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8045. Exceeding a junction temperature of 175C for an extended period of time can result in changes in silicon devices, potentially causing degradation or loss of functionality. MAXIMUM POWER DISSIPATION (Watts) 3.5 3.0 2.5 2.0 1.5 1.0 LFCSP 0.5 0.0 -40 04814-0-080 SOIC -20 0 20 40 60 80 AMBIENT TEMPERATURE (C) 100 120 Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation and loss of functionality. Rev. A | Page 5 of 24 AD8045 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS NC 8 +VS 7 OUTPUT 6 NC 5 BOTTOM VIEW (Not to Scale) NC = NO CONNECT AD8045 1 2 3 4 FEEDBACK -IN +IN 04814-0-003 +VS OUTPUT NC -VS 8 7 6 5 1 NC FEEDBACK -IN 04814-0-004 -VS BOTTOM VIEW (Not to Scale) 2 3 4 +IN NC = NO CONNECT Figure 5. SOIC Pin Configuration Figure 6 . 8-Lead LFCSP Pin Configuration Note: The exposed paddle must be connected to -VS or it must be electrically isolated (floating). Table 5. 8-Lead SOIC Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 Mnemonic FEEDBACK -IN +IN -VS NC OUTPUT +VS NC Exposed Paddle Description Feedback Pin Inverting Input Noninverting Input Negative Supply NC Output Positive Supply NC Must Be Connected to -VS or Electrically Isolated Table 6. 8-Lead LFCSP Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 Mnemonic NC FEEDBACK -IN +IN -VS NC OUTPUT +VS Exposed Paddle Description No Connect Feedback Pin Inverting Input Noninverting Input Negative Supply No Connect Output Positive Supply Must Be Connected to -VS or Electrically Isolated Rev. A | Page 6 of 24 AD8045 TYPICAL PERFORMANCE CHARACTERISTICS 1 VS = 5V RL = 1k G = +2 12 G = +2 11 VS = 5V RL = 1k 10 R = 499 F 18pF 10pF NORMALIZED CLOSED-LOOP GAIN (dB) 0 -1 -2 CLOSED-LOOP GAIN (dB) 9 8 7 6 5 4 3 2 G = +10 -3 -4 -5 -6 G = -1 5pF 0pF 1 04814-0-049 -7 1 10 100 FREQUENCY (MHz) 1000 0 10 100 FREQUENCY (MHz) 1000 Figure 7. Small Signal Frequency Response for Various Gains 4 G = +1 3 VS = 5V RS = 100 2 RL = 1k Figure 10. Small Signal Frequency Response for Various Capacitive Loads 4 G = +1 3 VS = 5V RL = 1k 2 RL = 500 CLOSED-LOOP GAIN (dB) CLOSED-LOOP GAIN (dB) 1 0 -1 -2 -3 -4 -5 04814-0-050 1 0 -1 -2 +125C -3 -4 -5 -40C RL = 100 -6 10 100 FREQUENCY (MHz) 1000 -6 10 100 FREQUENCY (MHz) 1000 Figure 8. Small Signal Frequency Response for Various Loads 5 G = +1 4 RL = 1k RS = 100 3 Figure 11. Small Signal Frequency Response for Various Temperatures 6.3 G = +2 VS = 5V RF = 499 6.2 R = 150 L VS = 2.5V CLOSED-LOOP GAIN (dB) 2 1 0 -1 -2 -3 -4 VS = 5V CLOSED-LOOP GAIN (dB) 6.1 VOUT = 2V p-p 6.0 VOUT = 200mV p-p 5.9 5.8 04814-0-051 -5 10 5.7 1 10 FREQUENCY (MHz) 100 100 FREQUENCY (MHz) 1000 Figure 9. Small Signal Frequency Response for Various Supplies Figure 12. 0.1 dB Flatness vs. Frequency for Various Output Voltages Rev. A | Page 7 of 24 04814-0-039 04814-0-052 +25C 04814-0-048 AD8045 2 1 0 G = +1 RL = 1k RS = 100 VOUT = 2V p-p 70 60 50 VS = 5V RL = 1k 0 -45 -90 -135 -180 -225 -270 -315 -360 0.1 1 10 FREQUENCY (MHz) 100 1000 04814-0-064 04814-0-028 04814-0-030 CLOSED-LOOP GAIN (dB) -1 -2 -3 -4 -5 -6 -7 -8 VS = 2.5V OPEN-LOOP GAIN (dB) VS = 5V 40 30 20 10 0 -9 04814-0-043 -10 10 100 FREQUENCY (MHz) 1000 -10 0.01 Figure 13. Large Signal Frequency Response for Various Supplies 2 1 0 -20 Figure 16. Open-Loop Gain and Phase vs. Frequency G = +1 VS = 5V RS = 100 VOUT = 2V p-p CLOSED-LOOP GAIN (dB) -1 -2 -3 -4 -5 -6 -7 -8 -9 04814-0-042 HARMONIC DISTORTION (dBc) G = +1 -30 VS = 5V VOUT = 2V p-p -40 RL = 1k RS = 100 -50 -60 -70 -80 HD3 SOIC AND LFCSP -90 -100 -110 -120 0.1 1 10 FREQUENCY (MHz) HD2 LFCSP HD2 SOIC RL = 1k RL = 100 -10 10 100 FREQUENCY (MHz) 1000 100 Figure 14. Large Signal Frequency Response for Various Loads 2 G = +2 Figure 17. Harmonic Distortion vs. Frequency for Various Packages -30 NORMALIZED CLOSED-LOOP GAIN (dB) 1 HARMONIC DISTORTION (dBc) 0 -1 -2 G = +10 -3 -4 -5 -6 V = 5V S RF = 499 -7 R = 1k L VOUT = 2V p-p -8 1 G = -1 G = +1 V = 5V -40 VS = 4V p-p OUT RL = 1k -50 -60 -70 -80 -90 -100 -110 HD2 SOIC HD2 LFCSP HD3 LFCSP AND SOIC 04814-0-041 10 100 FREQUENCY (MHz) 1000 -120 0.1 1 10 FREQUENCY (MHz) 100 Figure 15. Large Signal Frequency Response for Various Gains Figure 18. Harmonic Distortion vs. Frequency for Various Packages Rev. A | Page 8 of 24 OPEN-LOOP PHASE (Degrees) AD8045 -20 G = +1 V = 5V -30 S VOUT = 2V p-p RL = 100 -40 RS = 100 -50 -60 -70 HD2 SOIC -80 -90 -100 -110 0.1 HD2 LFCSP 04814-0-032 -30 HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) G = +2 VS = 5V -40 VOUT = 2V p-p RL = 150 R = 499 -50 F -60 HD2 SOIC -70 -80 HD2 LFCSP -90 -100 -110 0.1 04814-0-033 04814-0-025 04814-0-034 HD3 SOIC AND LFCSP 1 10 FREQUENCY (MHz) 100 HD3 SOIC AND LFCSP 1 10 FREQUENCY (MHz) 100 Figure 19. Harmonic Distortion vs. Frequency for Various Packages -20 Figure 22. Harmonic Distortion vs. Frequency for Various Packages -40 HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) G = -1 V = 5V -30 S VOUT = 2V p-p RL = 1k -40 SOIC AND LFCSP -50 -60 -70 -80 -90 HD3 -100 04814-0-036 G = +10 VS = 5V VOUT = 2V p-p -50 RL = 1k -60 HD2 LFCSP -70 -80 -90 -100 -110 0.1 HD2 SOIC HD2 HD3 SOIC AND LFCSP -110 0.1 1 10 FREQUENCY (MHz) 100 1 10 FREQUENCY (MHz) 100 Figure 20. Harmonic Distortion vs. Frequency for Various Packages -30 Figure 23. Harmonic Distortion vs. Frequency for Various Packages -50 G = +1 VS = 5V -60 RL = 1k RS = 100 f = 10MHz -70 HD3 SOIC AND LFCSP -80 -90 -100 HD2 SOIC -110 HD2 LFCSP 04814-0-037 G = -1 VS = 5V -40 RL = 150 VOUT = 2V p-p HARMONIC DISTORTION (dBc) -50 HD2 LFCSP -60 -70 -80 -90 -100 -110 0.1 HD3 SOIC AND LFCSP 1 10 FREQUENCY (MHz) 100 HD2 SOIC HARMONIC DISTORTION (dBc) -120 0 1 2 3 4 5 6 OUTPUT AMPLITUDE (V p-p) 7 8 Figure 21. Harmonic Distortion vs. Frequency for Various Packages Figure 24. Harmonic Distortion vs. Output Voltage for Various Packages Rev. A | Page 9 of 24 AD8045 -40 G = +1 VS = 5V RL = 150 -50 RS = 100 f = 10MHz -60 HD2 LFCSP -70 HD2 SOIC -80 -90 -100 HD3 SOIC AND LFCSP 04814-0-024 -30 G = +1 VS = 2.5 -40 VOUT = 2V p-p RL = 1k RS = 100 -50 -60 HD3 SOIC AND LFCSP -70 -80 HD2 LFCSP -90 -100 1 10 FREQUENCY (MHz) 100 HD2 SOIC 04814-0-029 04814-0-035 04814-0-031 HARMONIC DISTORTION (dBc) -110 0 1 2 3 4 5 6 OUTPUT AMPLITUDE (V p-p) 7 8 Figure 25. Harmonic Distortion vs. Output Voltage for Various Packages -40 HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) Figure 28. Harmonic Distortion vs. Frequency for Various Packages -20 HARMONIC DISTORTION (dBc) G = -1 VS = 5V -50 RL = 1k f = 10MHz SOIC AND LFCSP -60 -70 -80 HD2 -90 HD3 -100 -110 04814-0-026 G = +1 VS = 2.5V -30 VOUT = 2V p-p RL = 100 -40 RS = 100 -50 -60 HD3 SOIC AND LFCSP -70 -80 HD2 LFCSP -90 HD2 SOIC -100 1 10 FREQUENCY (MHz) 100 -120 0 1 2 3 4 5 6 OUTPUT VOLTAGE (V p-p) 7 8 Figure 26. Harmonic Distortion vs. Output Voltage -40 G = -1 VS = 5V -50 R = 150 L f = 10MHz -60 -70 HD2 SOIC -80 -90 HD3 SOIC AND LFCSP -100 -110 04814-0-027 Figure 29. Harmonic Distortion vs. Frequency for Various Packages -20 G = -1 VS = 2.5V -30 VOUT = 2V p-p RL = 1k SOIC AND LFCSP -40 -50 -60 HD3 -70 -80 HD2 -90 -100 0.1 HARMONIC DISTORTION (dBc) HD2 LFCSP -120 0 1 2 3 4 5 6 OUTPUT VOLTAGE (V p-p) 7 8 HARMONIC DISTORTION (dBc) 1 10 FREQUENCY (MHz) 100 Figure 27. Harmonic Distortion vs. Output Voltage Figure 30. Harmonic Distortion vs. Frequency for Various Packages Rev. A | Page 10 of 24 AD8045 -40 -50 G = +1 VS = +5V RL = 1k RS = 100 f = 10MHz 0.15 RS = 100 RL = 150 G = +1 0.10 V = 2.5 S OR VS = 5V HARMONIC DISTORTION (dBc) OUTPUT VOLTAGE (V) 04814-0-022 -60 HD3 SOIC AND LFCSP -70 -80 -90 -100 HD2 LFCSP -110 0.5 0.05 0 -0.05 HD2 SOIC -0.10 -0.15 0 5 10 TIME (ns) 15 20 25 1.0 1.5 2.0 OUTPUT VOLTAGE (V p-p) 2.5 3.0 Figure 31. Harmonic Distortion vs. Output Voltage for Various Packages -40 G = +1 VS = +5V -50 RL = 150 RS = 100 f = 10MHz -60 -70 HD3 SOIC AND LFCSP -80 -90 -100 HD2 SOIC -110 0.5 0.7 0.9 HD2 LFCSP 04814-0-023 Figure 34. Small Signal Transient Response for Various Supplies and Loads 0.15 HARMONIC DISTORTION (dBc) RL = 1k CL = 10pF RSNUB = 30 0.10 V = 5V S G = +1 OUTPUT VOLTAGE (V) 0.05 0 -0.05 RSNUB 30 CL 10pF RL 1k 04814-0-013 04814-0-014 -0.10 -0.15 0 5 10 TIME (ns) 15 20 25 1.1 1.3 1.5 1.7 1.9 OUTPUT VOLTAGE (V p-p) 2.1 2.3 2.5 Figure 32. Harmonic Distortion vs. Output Voltage for Various Packages 1600 1400 1200 Figure 35. Small Signal Transient Response for Various Supplies and Loads 0.15 RL = 1k VS = 5V POSITIVE SLEW RATE 0.10 NEGATIVE SLEW RATE VS = 2.5V G = +2 RC = 1k OR RC = 150k OUTPUT VOLTAGE (V) SLEW RATE (V/s) 0.05 1000 800 600 400 200 0 0 1 2 3 OUTPUT VOLTAGE STEP (V) 4 5 04814-0-076 0 -0.05 -0.10 -0.15 0 5 10 TIME (ns) 15 20 25 Figure 33. Slew Rate vs. Output Voltage Figure 36. Small Signal Transient Response for Various Loads Rev. A | Page 11 of 24 04814-0-012 AD8045 0.20 18pF 0.15 0.10 2 1 0 -1 0pF -2 -3 04814-0-015 3 VS = 5V RL = 1k G = +2 OUTPUT VOLTAGE (V) 0.05 0 -0.05 -0.10 -0.15 G = +2 VS = 5V RL = 1k -0.20 0 5 OUTPUT VOLTAGE (V) 0pF 10pF 18pF -4 0 5 10 TIME (ns) 15 20 25 10 TIME (ns) 15 20 25 Figure 37. Small Signal Transient Response with Capacitive Load 3 Figure 40. Large Signal Transient Response with Capacitive Load 3 2 VS = 5V RS = 100 G = +2 2 LOAD = 1k OR 150 OUTPUT VOLTAGE (V) 1 OUTPUT VOLTAGE (V) 1 0 0 -1 -1 -2 -2 04814-0-016 -3 0 5 10 TIME (ns) 15 20 25 -3 0 5 10 TIME (ns) 15 20 25 Figure 38. Large Signal Transient Response for Various Loads 3 6 Figure 41. Large Signal Transient Response, Inverting INPUT AND OUTPUT VOLTAGE (V) 2 RL = 1k RS = 100 G = +1 VS = 5V G = +1 5 VS = 5V f = 5MHz 4 3 2 1 0 -1 -2 -3 -4 -5 OUTPUT INPUT OUTPUT VOLTAGE (V) 1 VS = 2.5V 0 -1 -2 04814-0-017 -3 0 5 10 TIME (ns) 15 20 25 -6 0 20 40 60 80 100 120 TIME (ns) 140 160 180 200 Figure 39. Large Signal Transient Response for Various Supplies Figure 42. Input Overdrive Recovery Rev. A | Page 12 of 24 04814-0-061 04814-0-019 G = -1 VS = 5V RL = 1k 04814-0-018 AD8045 6 G = +2 5 VS = 5V f = 5MHz 4 3 2 1 0 -1 -2 -3 -4 -5 04814-0-062 0 2 x INPUT -10 VS = 5V INPUT AND OUTPUT VOLTAGE (V) POWER SUPPLY REJECTION (dB) -20 -30 -PSR -40 +PSR -50 -60 -70 -80 0.01 04814-0-045 04814-0-054 04814-0-020 OUTPUT -6 0 20 40 60 80 100 120 TIME (ns) 140 160 180 200 0.1 1 10 FREQUENCY (MHz) 100 1000 Figure 43. Output Overdrive Recovery 100 -30 Figure 46. Power Supply Rejection vs. Frequency VS = 5V RF = 499 COMMON-MODE REJECTION (dB) 04814-0-053 -40 VOLTAGE NOISE (nV/ Hz) -50 10 -60 -70 -80 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 1G -90 0.1 1 10 FREQUENCY (MHz) 100 1000 Figure 44. Voltage Noise vs. Frequency 100 100k Figure 47. Common-Mode Rejection vs. Frequency VS = 5V G = +1 CLOSED-LOOP INPUT IMPEDANCE () 04814-0-078 CURRENT NOISE (pA/ Hz) 10k 10 1000 100 1 100 10 1 10 100 FREQUENCY (MHz) 1000 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M Figure 45. Current Noise vs. Frequency Figure 48. Input Impedance vs. Frequency Rev. A | Page 13 of 24 AD8045 1000 CLOSED-LOOP OUTPUT IMPEDANCE () G = +1 VS = 5V 100 100 VS = 5V N = 450 X = 50V = 180V 80 10 1 COUNT 0.1 60 40 20 0.01 1 10 100 FREQUENCY (MHz) 1000 04814-0-055 0 -900 -600 -300 0 VOFFSET (V) 300 600 900 Figure 49. Output Impedance vs. Frequency 50 48 G = +10 VS = 5V RL = 1k Figure 52. VOS Distribution for VS = 5 V VS = +5V N = 450 X = 540V = 195V 80 THIRD-ORDER INTERCEPT (dBm) 46 44 42 40 38 36 34 32 30 5 10 20 FREQUENCY (MHz) 30 40 04814-0-040 60 COUNT 40 20 0 -300 0 300 600 VOFFSET (V) 900 1200 1500 Figure 50. Third-Order Intercept vs. Frequency 0 -0.02 -0.04 G = +2 VS = 5V GAIN 0.25 500 300 Figure 53. VOS Distribution for VS = +5 V DIFFERENTIAL PHASE (Degrees) 0.20 100 DIFFERENTIAL GAIN (%) OFFSET VOLTAGE (V) -0.06 -0.08 -0.10 -0.12 -0.14 -0.16 -0.18 PHASE 0.05 0.10 0.15 VS = +5V -100 -300 -500 -700 -900 VS = 5V 04814-0-021 -0.20 1 NUMBER OF 150 LOADS 0 10 -1100 -40 -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125 Figure 51. Differential Gain and Phase vs. Number of 150 Loads Figure 54. Offset Voltage vs. Temperature for Various Supplies Rev. A | Page 14 of 24 04814-0-058 04814-0-077 04814-0-063 AD8045 -1.0 -1.2 -1.4 1.5 +VS - VOUT -1.6 -1.8 -2.0 -2.2 -2.4 IB+, VS = 5V IB-, VS = 5V OUTPUT SATURATION VOLTAGE (V) 1.0 INPUT BIAS CURRENT (A) 0.5 VS = 5V 0 VS = +5V IB-, VS = 5V IB+, VS = 5V -0.5 -2.6 -2.8 04814-0-059 -1.0 -VS - VOUT -1.5 0.1 04814-0-044 04814-0-046 04814-0-047 -3.0 -40 -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125 1 LOAD (k) 10 Figure 55. Input Bias Current vs. Temperature for Various Supplies 1.20 VS = 5V RL = 1k Figure 58. Output Saturation Voltage vs. Load for Various Supplies 4 3 2 OUTPUT SATURATION VOLTAGE (V) 1.15 -VS + VOUT 1 1.10 1.05 VS = 5V VOS (mV) 0 -1 -2 -3 RL = 150 RL = 1k 1.00 +VS - VOUT +VS - VOUT -VS + VOUT 0.95 0.90 -40 04814-0-057 -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125 -4 -4 -3 -2 -1 0 VOUT (V) 1 2 3 4 Figure 56. Output Saturation Voltage vs. Temperature for Various Supplies 17.0 Figure 59. Input Offset Voltage vs. Output Voltage for Various Loads 0.30 G = +2 VS = 5V VOUT = 2V p-p RL = 150 RF = 499 16.5 0.20 SUPPLY CURRENT (mA) VS = 5V 16.0 VS = 5V 15.5 0.10 SETTLING (%) 04814-0-056 0 -0.10 15.0 -0.20 14.5 -40 -0.30 0 2.5 5.0 7.5 10.0 12.5 TIME (ns) 15.0 17.5 20.0 22.5 -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125 Figure 57. Supply Current vs. Temperature for Various Supplies Figure 60. Short Term 0.1% Settling Time Rev. A | Page 15 of 24 AD8045 CIRCUIT CONFIGURATIONS WIDEBAND OPERATION Figure 61 and Figure 62 show the recommended circuit configurations for noninverting and inverting amplifiers. In unity gain (G = +1) applications, RS helps to reduce high frequency peaking. It is not needed for any other configurations. For more information on layout, see the Printed Circuit Board Layout section. The resistor at the output of the amplifier, labeled RSNUB, is used only when driving large capacitive loads. Using RSNUB improves stability and minimizes ringing at the output. For more information, see the Driving Capacitive Loads section. RF +VS 10F + 0.1F RG RF +VS 10F + 0.1F VIN RG AD8045 0.1F RSNUB VOUT 10F + -VS Figure 62. Inverting Configuration VIN RS AD8045 0.1F RSNUB VOUT 10F + -VS Figure 61. Noninverting Configuration 04814-0-074 Rev. A | Page 16 of 24 04814-0-075 R = RG||RF AD8045 THEORY OF OPERATION The AD8045 is a high speed voltage feedback amplifier fabricated on ADI's second generation eXtra Fast Complementary Bipolar (XFCB) process. An H-bridge input stage is used to attain a 1400 V/s slew rate and low distortion in addition to a low 3 nV/Hz input voltage noise. Supply current and offset voltage are laser trimmed for optimum performance. RS VIN + VOUT - RF RG 04814-0-009 FREQUENCY RESPONSE The AD8045's open-loop response over frequency can be approximated by the integrator response shown in Figure 63. Figure 64. Noninverting Configuration DC ERRORS VIN VOUT Figure 65 shows the dc error contributions. The total output error voltage is VOUT/VIN (dB) R +R R +R VOUT (ERROR)= -I B+ RS G F + I B- RF + VOS G F RG RG RS VOS IB+ IB- 04814-0-008 VOUT/VIN = fCROSSOVER f 10 100 FREQUENCY (MHz) fCROSSOVER = 400MHz + VOUT - 0 1 1000 RF RG 04814-0-010 Figure 63. Open-Loop Response The closed-loop transfer function for the noninverting configuration is shown in Figure 64 and is written as Figure 65. Amplifier DC Errors 2 x f CROSSOVER x (RG + RF ) VOUT = (RF + RG )s + 2 x f CROSSOVER x RG VIN where: s is (2 j)f. fCROSSOVER is the frequency where the amplifier's open-loop gain equals 1 (0 dB). DC gain is therefore VOUT (RG + RF ) = VIN RG The voltage error due to IB+ and IB- is minimized if RS = RF||RG. To include the effects of common-mode and power supply rejection, model VOS as VOS = VOS nom + VS VCM + PSR CMR where: Vos nom is the offset voltage at nominal conditions. VS is the change in the power supply voltage from nominal conditions. PSR is the power supply rejection. Closed-loop -3 dB bandwidth equals VOUT RG = f CROSSOVER x (RG + RF ) VIN CMR is the common-mode rejection. VCM is the change in common-mode voltage from nominal conditions. The closed-loop bandwidth is inversely proportional to the noise gain of the op amp circuit, (RF + RG)/RG. This simple model can be used to predict the -3 dB bandwidth for noise gains above +2. The actual bandwidth of circuits with noise gains at or below +2 is higher due to the influence of other poles present in the real op amp. Rev. A | Page 17 of 24 AD8045 OUTPUT NOISE Figure 66 shows the contributors to the noise at the output of a noninverting configuration. VRS RS IEN+ IEN- VEN + VOUT - Ven , IN+, and IN- are due to the amplifier. VR F , VRG , and VR S are due to the feedback network resistors. RG and RF, and source resistor, RS. Total output voltage noise, VOUT _ EN , is the rms sum of all the contributions. VOUT _ EN = (Gn x Ven)2 + (IN + x RS x Gn )2 + (IN - x RF||RG x Gn )2 + 4kTR f + 4kTRG (Gn )2 + 4kTRS (Gn )2 VRF RF where: 04814-0-011 RG VRG Gn is the noise gain RF + RG . RG Figure 66. Amplifier DC Errors Ven is the op amp input voltage noise. IN is the op amp input current noise. Table 7 lists the expected output voltage noise spectral density for several gain configurations. Table 7. Noise and Bandwidth for Various Gains -3 dB Bandwidth1 1 GHz 400 MHz 90 MHz 40 MHz 300 MHz Output Noise (nV/Hz) 3.3 7.4 16.4 31 7.4 Gain +1 +2 +5 +10 -1 RF 0 499 499 499 499 RG - 499 124 56 499 RS 100 0 0 0 N/A 1 RL = 1 k. Rev. A | Page 18 of 24 AD8045 APPLICATIONS LOW DISTORTION PINOUT The AD8045 LFCSP package features Analog Devices new low distortion pinout. The new pinout provides two advantages over the traditional pinout. First, improved second harmonic distortion performance, which is accomplished by the physical separation of the noninverting input pin and the negative power supply pin. Second, the simplification of the layout due to the dedicated feedback pin and easy routing of the gain set resistor back to the inverting input pin. This allows a compact layout, which helps to minimize parasitics and increase stability. The traditional SOIC pinout has been slightly modified as well to incorporate a dedicated feedback pin. Pin 1, previously a no connect pin on the amplifier, is now a dedicated feedback pin. The new pinout reduces parasitics and simplifies the board layout. Existing applications that use the traditional SOIC pinout can take full advantage of the outstanding performance offered by the AD8045. An electrical insulator may be required if the SOIC rests on the ground plane or other metal trace. This is covered in more detail in the Exposed Paddle section of this data sheet. In existing designs, which have Pin 1 tied to ground or to another potential, simply lift Pin 1 of the AD8045 or remove the potential on the Pin 1 solder pad. The designer does not need to use the dedicated feedback pin to provide feedback for the AD8045. The output pin of the AD8045 can still be used to provide feedback to the inverting input of the AD8045. This dc-coupled differential driver is best suited for 5 V operation in which optimum distortion performance is required and the input signal is ground referenced. 511 511 AD8045 VCML - VIN 33 VINA VIN 511 511 511 511 20pF VCML + VIN 33 VINB AD9244 AD8045 511 511 2.5k 0.1F 100 0.1F 1F OP27 Figure 67. High Speed ADC Driver The outputs of the AD8045s are centered about the AD9244's common-mode range of 2.5 V. The common-mode reference voltage from the AD9244 is buffered and filtered via the OP27 and fed to the noninverting resistor network used in the level shifting circuit. The spurious-free dynamic range (SFDR) performance is shown in Figure 68. Figure 69 shows a 50 MHz single-tone FFT performance. 120 HIGH SPEED ADC DRIVER When used as an ADC driver, the AD8045 offers results comparable to transformers in distortion performance. Many ADC applications require that the analog input signal be dc-coupled and operate over a wide frequency range. Under these requirements, operational amplifiers are very effective interfaces to ADCs. An op amp interface provides the ability to amplify and level shift the input signal to be compatible with the input range of the ADC. Unlike transformers, operational amplifiers can be operated over a wide frequency range down to and including dc. Figure 67 shows the AD8045 as a dc-coupled differential driver for the AD9244, a 14-bit 65 MSPS ADC. The two amplifiers are configured in noninverting and inverting modes. Both amplifiers are set with a noise gain of +2 to provide better bandwidth matching. The inverting amplifier is set for a gain of -1, while the noninverting is set for a gain of +2. The noninverting input is divided by 2 in order to normalize its output and make it equal to the inverting output. 100 AD8045 80 SFDR (dBc) 60 40 20 0 1 10 INPUT FREQUENCY (MHz) 100 Figure 68. SFDR vs. Frequency Rev. A | Page 19 of 24 04814-0-067 04814-0-066 CML AD8045 0 -20 AIN = -1dBFS SNR = 69.9dBc SFDR = 65.3dBc DISTORTION (dBc) -40 Setting the resistors and capacitors equal to each other greatly simplifies the design equations for the Sallen-Key filter. The corner frequency, or -3 dB frequency, can be described by the equation fc = -60 1 2RC -80 The quality factor, or Q, is shown in the equation Q= 04814-0-068 -100 1 3-K -120 0 5 10 15 20 FREQUENCY (MHz) 25 30 The gain, or K, of the circuits are First Stage K = R8 R3 + 1, Second Stage K = +1 R7 R4 Figure 69. Single-Tone FFT, FIN = 50 MHz, Sample Rate = 65 MSPS Shown in the First Nyquist Zone 90 MHZ ACTIVE LOW-PASS FILTER (LPF) Active filters are used in many applications such as antialiasing filters and high frequency communication IF strips. With a 400 MHz gain bandwidth product and high slew rate, the AD8045 is an ideal candidate for active filters. Figure 70 shows the frequency response of the 90 MHz LPF. In addition to the bandwidth requirements, the slew rate must be capable of supporting the full power bandwidth of the filter. In this case, a 90 MHz bandwidth with a 2 V p-p output swing requires at least 1200 V/s. This performance is achievable only at 90 MHz because of the AD8045's wide bandwidth and high slew rate. The circuit shown in Figure 73 is a 90 MHz, 4-pole, Sallen-Key, LPF. The filter comprises two identical cascaded Sallen-Key LPF sections, each with a fixed gain of G = +2. The net gain of the filter is equal to G = +4 or 12 dB. The actual gain shown in Figure 70 is only 6 dB. This is due to the output voltage being divided in half by the series matching termination resistor, RT, and the load resistor. Resistor values are kept low for minimal noise contribution, offset voltage, and optimal frequency response. Due to the low capacitance values used in the filter circuit, the PCB layout and minimization of parasitics is critical. A few picofarads can detune the filters corner frequency, fc. The capacitor values shown in Figure 73 actually incorporate some stray PCB capacitance. Capacitor selection is critical for optimal filter performance. Capacitors with low temperature coefficients, such as NPO ceramic capacitors and silver mica, are good choices for filter elements. 20 10 0 -10 -20 GAIN (dB) -30 -40 -50 -60 -70 -80 -90 0.1 1 10 FREQUENCY (MHz) 100 1000 04814-0-006 Figure 70. 90 MHz Low-Pass Filter Response Rev. A | Page 20 of 24 AD8045 1 1 04814-0-069 CH1 50.0mV M4.00ns A CH1 0.00V CH1 500mV M4.00ns A CH1 0.00V Figure 71. Small Signal Transient Response of 90 MHz LPF Figure 72. Large Signal Transient Response of 90 MHz LPF C1 7.1pF C3 7.1pF +5V 10F +5V 10F INPUT RT 49.9 R1 249 R2 249 C2 7.1pF 0.1F U1 R6 249 10F R5 249 C4 7.1pF 0.1F U1 RT 49.9 10F OUTPUT R9 24.9 C5 5pF 04814-0-005 0.1F 0.1F -5V R4 499 R3 499 -5V R7 499 R8 499 Figure 73. 4-Pole, 90 MHz, Sallen-Key Low-Pass Filter Rev. A | Page 21 of 24 04814-0-070 AD8045 PRINTED CIRCUIT BOARD LAYOUT Laying out the printed circuit board (PCB) is usually the last step in the design process and often proves to be one of the most critical. A brilliant design can be rendered useless because of a poor or sloppy layout. Since the AD8045 can operate into the RF frequency spectrum, high frequency board layout considerations must be taken into account. The PCB layout, signal routing, power supply bypassing, and grounding all must be addressed to ensure optimal performance. requirements. Additional smaller value capacitors help to provide a low impedance path for unwanted noise out to higher frequencies but are not always necessary. Placement of the capacitor returns (grounds), where the capacitors enter into the ground plane, is also important. Returning the capacitors grounds close to the amplifier load is critical for distortion performance. Keeping the capacitors distance short, but equal from the load, is optimal for performance. In some cases, bypassing between the two supplies can help to improve PSRR and to maintain distortion performance in crowded or difficult layouts. It is brought to the designer's attention here as another option to improve performance. Minimizing the trace length and widening the trace from the capacitors to the amplifier reduce the trace inductance. A series inductance with the parallel capacitance can form a tank circuit, which can introduce high frequency ringing at the output. This additional inductance can also contribute to increased distortion due to high frequency compression at the output. The use of vias should be minimized in the direct path to the amplifier power supply pins since vias can introduce parasitic inductance, which can lead to instability. When required, use multiple large diameter vias because this lowers the equivalent parasitic inductance. SIGNAL ROUTING The AD8045 LFCSP features the new low distortion pinout with a dedicated feedback pin and allows a compact layout. The dedicated feedback pin reduces the distance from the output to the inverting input, which greatly simplifies the routing of the feedback network. When laying out the AD8045 as a unity gain amplifier, it is recommended that a short, but wide, trace between the dedicated feedback pin and the inverting input to the amplifier be used to minimize stray parasitic inductance. To minimize parasitic inductances, ground planes should be used under high frequency signal traces. However, the ground plane should be removed from under the input and output pins to minimize the formation of parasitic capacitors, which degrades phase margin. Signals that are susceptible to noise pickup should be run on the internal layers of the PCB, which can provide maximum shielding. GROUNDING The use of ground and power planes is encouraged as a method of proving low impedance returns for power supply and signal currents. Ground and power planes can also help to reduce stray trace inductance and to provide a low thermal path for the amplifier. Ground and power planes should not be used under any of the pins of the AD8045. The mounting pads and the ground or power planes can form a parasitic capacitance at the amplifiers input. Stray capacitance on the inverting input and the feedback resistor form a pole, which degrades the phase margin, leading to instability. Excessive stray capacitance on the output also forms a pole, which degrades phase margin. POWER SUPPLY BYPASSING Power supply bypassing is a critical aspect of the PCB design process. For best performance, the AD8045 power supply pins need to be properly bypassed. A parallel connection of capacitors from each of the power supply pins to ground works best. Paralleling different values and sizes of capacitors helps to ensure that the power supply pins "see" a low ac impedance across a wide band of frequencies. This is important for minimizing the coupling of noise into the amplifier. Starting directly at the power supply pins, the smallest value and sized component should be placed on the same side of the board as the amplifier, and as close as possible to the amplifier, and connected to the ground plane. This process should be repeated for the next larger value capacitor. It is recommended for the AD8045 that a 0.1 F ceramic 0508 case be used. The 0508 offers low series inductance and excellent high frequency performance. The 0.1 F case provides low impedance at high frequencies. A 10 F electrolytic capacitor should be placed in parallel with the 0.1 F. The 10 f capacitor provides low ac impedance at low frequencies. Smaller values of electrolytic capacitors may be used depending on the circuit Rev. A | Page 22 of 24 AD8045 EXPOSED PADDLE The AD8045 features an exposed paddle, which lowers the thermal resistance by 25% compared to a standard SOIC plastic package. The exposed paddle of the AD8045 is internally connected to the negative power supply pin. Therefore, when laying out the board, the exposed paddle must either be connected to the negative power supply or left floating (electrically isolated). Soldering the exposed paddle to the negative power supply metal ensures maximum thermal transfer. Figure 74 and Figure 75 show the proper layout for connecting the SOIC and LFCSP exposed paddle to the negative supply. THERMAL CONDUCTIVE INSULATOR 04814-0-072 Figure 76. SOIC with Thermal Conductive Pad Material The thermal pad provides high thermal conductivity but isolates the exposed paddle from ground or other potential. It is recommended, when possible, to solder the paddle to the negative power supply plane or trace for maximum thermal transfer. Note that soldering the paddle to ground shorts the negative power supply to ground and can cause irreparable damage to the AD8045. DRIVING CAPACITIVE LOADS 04814-0-071 Figure 74. SOIC Exposed Paddle Layout The use of thermal vias or "heat pipes" can also be incorporated into the design of the mounting pad for the exposed paddle. These additional vias help to lower the overall theta junction to ambient (JA). Using a heavier weight copper on the surface to which the amplifier's exposed paddle is soldered can greatly reduce the overall thermal resistance "seen" by the AD8045. In general, high speed amplifiers have a difficult time driving capacitive loads. This is particularly true in low closed-loop gains, where the phase margin is the lowest. The difficulty arises because the load capacitance, CL, forms a pole with the output resistance, RO, of the amplifier. The pole can be described by the equation fP = 1 2RO C L If this pole occurs too close to the unity gain crossover point, the phase margin degrades. This is due to the additional phase loss associated with the pole. The AD8045 output can drive 18 pF of load capacitance directly, in a gain of +2 with 30% overshoot, as shown in Figure 37. Larger capacitance values can be driven but must use a snubbing resistor (RSNUB) at the output of the amplifier, as shown in Figure 61 and Figure 62. Adding a small series resistor, RSNUB, creates a zero that cancels the pole introduced by the load capacitance. Typical values for RSNUB can range from 25 to 50 . The value is typically arrived at empirically and based on the circuit requirements. Figure 75. LFCSP Exposed Paddle Layout For existing designs that want to incorporate the AD8045, electrically isolating the exposed paddle is another option. If the exposed paddle is electrically isolated, the thermal dissipation is primarily through the leads, and the thermal resistance of the package now approaches 125C/W, the standard SOIC JA. However, a thermally conductive and electrically isolated pad material may be used. A thermally conductive spacer, such as the Bergquist Company's Sil-Pad, is an excellent solution to this problem. Figure 76 shows a typical implementation using thermal pad material. 04814-0-073 Rev. A | Page 23 of 24 AD8045 OUTLINE DIMENSIONS 4.00 (0.157) 3.90 (0.154) 3.80 (0.150) 5.00 (0.197) 4.90 (0.193) 4.80 (0.189) 8 1 5 4 BOTTOM VIEW (PINS UP) 2.29 (0.092) 6.20 (0.244) 6.00 (0.236) 5.80 (0.228) 2.29 (0.092) TOP VIEW 1.27 (0.05) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY SEATING 0.10 PLANE 1.75 (0.069) 1.35 (0.053) 0.50 (0.020) x 45 0.25 (0.010) 0.51 (0.020) 0.31 (0.012) 8 0.25 (0.0098) 0 1.27 (0.050) 0.40 (0.016) 0.17 (0.0068) COMPLIANT TO JEDEC STANDARDS MS-012 CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 77. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP], Narrow Body (RD-8-1)--Dimensions shown in millimeters and (inches) 0.50 0.40 0.30 3.00 BSC SQ 0.45 0.60 MAX PIN 1 INDICATOR 8 1 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ 0.50 BSC 5 (BOTTOM VIEW) EXPOSED PAD 1.50 REF 4 1.90 1.75 1.60 0.90 0.85 0.80 12 MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF 0.25 MIN 1.60 1.45 1.30 SEATING PLANE Figure 78. 8-Lead Lead Frame Chip Scale Package [LFCSP], 3 mm x 3 mm Body (CP-8-2)--Dimensions shown in millimeters ORDERING GUIDE Model AD8045ARD AD8045ARD-REEL AD8045ARD-REEL7 AD8045ARDZ1 AD8045ARDZ-REEL1 AD8045ARDZ-REEL71 AD8045ACP-R2 AD8045ACP-REEL AD8045ACP-REEL7 AD8045ACPZ-R21 AD8045ACPZ-REEL1 AD8045ACPZ-REEL71 Minimum Ordering Quantity 1 2,500 1,000 1 2,500 1,000 250 5,000 1,500 250 5,000 1,500 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead LFCSP 8-Lead LFCSP 8-Lead LFCSP 8-Lead LFCSP 8-Lead LFCSP 8-Lead LFCSP Package Option RD-8-1 RD-8-1 RD-8-1 RD-8-1 RD-8-1 RD-8-1 CP-8-2 CP-8-2 CP-8-2 CP-8-2 CP-8-2 CP-8-2 Branding H8B H8B H8B H8B H8B H8B 1 Z = Pb-free part. (c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04814-0-9/04(A) Rev. A | Page 24 of 24 This datasheet has been download from: www..com Datasheets for electronics components. |
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